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C8051F380/1/2/3/4/5/6/7/C
USB Register Definition 21.8. POWER: USB0 Power
Bit
Name
Type
Reset
7
ISOUD
R/W
0
6
R/W
0
5
R/W
0
4
USBINH
R/W
0
3
USBRST
R/W
0
2
RESUME
R/W
0
1
SUSMD
R
0
0
SUSEN
R/W
0
USB Register Address = 0x01
Bit Name
Function
7
6:5
ISOUD
Unused
ISO Update Bit.
This bit affects all IN Isochronous endpoints.
0: When software writes INPRDY = 1, USB0 will send the packet when the next IN token
is received.
1: When software writes INPRDY = 1, USB0 will wait for a SOF token before sending the
packet. If an IN token is received before a SOF token, USB0 will send a zero-length data
packet.
Read = 00b. Write = don’t care.
4
USBINH USB0 Inhibit Bit.
This bit is set to 1 following a power-on reset (POR) or an asynchronous USB0 reset.
Software should clear this bit after all USB0 transceiver initialization is complete. Soft-
ware cannot set this bit to 1.
0: USB0 enabled.
1: USB0 inhibited. All USB traffic is ignored.
3
USBRST Reset Detect.
Read:
Write:
0: Reset signaling is not present. Writing 1 to this bit forces an
1: Reset signaling detected on
the bus.
asynchronous USB0 reset.
2
1
RESUME Force Resume.
Writing a 1 to this bit while in Suspend mode (SUSMD = 1) forces USB0 to generate
Resume signaling on the bus (a remote wakeup event). Software should write RESUME
= 0 after 10 to 15 ms to end the Resume signaling. An interrupt is generated, and hard-
ware clears SUSMD, when software writes RESUME = 0.
SUSMD Suspend Mode.
Set to 1 by hardware when USB0 enters suspend mode. Cleared by hardware when soft-
ware writes RESUME = 0 (following a remote wakeup) or reads the CMINT register after
detection of Resume signaling on the bus.
0: USB0 not in suspend mode.
1: USB0 in suspend mode.
0
SUSEN
Suspend Detection Enable.
0: Suspend detection disabled. USB0 will ignore suspend signaling on the bus.
1: Suspend detection enabled. USB0 will enter suspend mode if it detects suspend sig-
naling on the bus.
Rev. 1.4
185
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